Peripheral Component Interconnect Express (PCIe) is a modern, high speed standard for a serial computer expansion bus. It operates more effectively and efficiently than other older, conventional buses in part because of its bus topology. While standard buses (such as PCI) use a shared parallel bus architecture, in which the PCI host and all devices share a common set of address, data and control lines, PCIe is based on point-to-point topology, with separate serial links connecting every device to the root complex (host). The conventional PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCIe bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.
Typically, a PCIe bus allows one device each on each endpoint of each connection. PCIe switches can create multiple endpoints out of one endpoint to allow sharing one endpoint with multiple devices.
A traditional PCIe switch can switch transaction layer packets (TLPs) from an uplink port to a downlink port based on address or requirement identifier (Req ID) only. However, as fields advance and require more robust communication, the conventional techniques for relaying information become increasingly inefficient and require improvement.